The present invention concerns personal computers and pertains particularly to a direct memory access controller with full read/write capability.
The standard personal computer (PC) architecture facilitates data movement between an input/output (I/O) device and system memory by providing a hardware mechanism entitled Direct Memory Access (DMA). This hardware method of data transfer allows data to be read from an I/O device and written to a designated location in memory, or read from a designated location in memory and written to an I/O device without involvement by a central processing unit (CPU). This functionality in the PC architecture is basically a legacy feature from a time when hardware controlled system data transfers were usually faster than the comparatively slower CPU transfers.
Software compatibility issues currently requires that DMA functionality be propagated in current PC system designs to ensure older software execution on current machines. In the PC architecture the DMA process is administered by three controller chips: two 8237 DMA controllers, and an associated 74LS612 page register chip. These chips are available, for example, from VLSI Technology, Inc., having a business address of 1109 McKay Drive, San Jose, Calif. 95131.
In an integrated device, such as an application specific integrated circuit (ASIC) or PC core logic device, the DMA controllers and page registers exist as functional blocks. The page registers do not affect the actual control of the DMA transfer but simply hold the address of the memory page to be accessed and drive this information onto the address bus when appropriate.
Working in concert the two DMA controllers provide eight DMA channels that can address up to 16 megabytes of memory. Channels zero through three are eight bit (1 byte) channels, and channels four through seven are 16 bit (2 byte) channels. Once configured by software, the DMA controller is free to move "blocks" of data as small as a single byte or as large 64 kilobytes, the largest number programmable in the word count register for each channel. Each data move is referred to as a "transfer" and each transfer consist of one or more data transfer cycles that may be either a single byte or two bytes in size (i.e., 8 bit or 16 bits), depending upon the DMA channel selected.
Each transfer is initiated by a device asserting a DREQ signal associated with a specific channel to request the DMA transfer for that channel. The DMA controller arbitrates for control of the system and places the CPU in a hold state, and then returns an acknowledge signal, DACK, to the requesting device. The DMA controller then executes the DMA transfer according to the configuration set in the associated registers for the specific channel. The eight channels are independent and are set up on a rotating priority scheme so that only one specific channel is transferring data at a time.
Each channel in the DMA controller can be set to one of three modes of data transfer: Single, Block and Demand mode. Single mode permits a single transfer from the requesting I/O device to or from the specified memory address. Block mode permits a block of data to be transferred of a size specified by a value programmed into the DMA controller. Demand mode is similar to Block mode except that the transfer may be started, stopped, and restarted by asserting and de-asserting the DREQ.
Each of the three modes can be divided further into a transfer type. The available transfer types are: Read transfer that moves data from memory to the I/O device by asserting MEMR# and IOW#; Write transfer that moves data from the I/O device to memory by asserting MEMW# and IOR#; and a Verify transfers which are "pseudo transfers" that function the same as the Read and Write, except that the memory and I/O command lines remain inactive. A fourth type of transfer, memory-to-memory, also exists.
Historically, DMA systems in the PC architectures have functioned under the assumption that DMA transactions will always be permitted to proceed to completion and that a need to interrupt a DMA cycle prior to completion did not truly exist. However, with the advent of power management strategies and the implementation of "suspend" or "sleep" mode states in computers, it is now desirable to facilitate an interruption to a DMA transaction prior to completion. Such a situation presents a problem for a DMA architecture using DMA controllers as currently implemented. That is, currently, DMA controllers are not designed to permit such an interruption nor to facilitate restoration of system conditions to permit completion of an interrupted DMA cycle.